Semiconductor manufacturing is known to improve device density in an exponential manner over time, but such improvements do come with a price. The cost of a mask set required for each new process technology has also been increasing exponentially. While 20 years ago the mask set cost was less than $20,000, it quite common today to cost more than $1M for a state-of-the-art device mask set. These changes represent an increasing challenge primarily to custom products, which tend to target smaller volume and less diverse markets therefore making the increased cost of product development very hard to accommodate.
Custom Integrated Circuits (CICs) can be segmented into two groups. The first group includes devices that have all their layers custom made. The second group includes devices that have at least some generic layers used across the different custom products. Well known examples of the second group include Gate Arrays, which use generic layers for layers up to the contact layer, and field-programmable gate arrays (FPGAs), which utilize generic layers for all their layers. The generic layers in such devices are generally a repeating pattern structure in an array form. Logic array technology is based on a generic fabric that is customized for a specific design during the customization stage. For FPGAs, the customization is done through programming by electrical signals.
The most common FPGAs on the market today are based on static random access memories (SRAMs) as the programming elements. Floating-Gate Flash programmable elements are also utilized to some extent. Less commonly, FPGAs use an antifuse approach as the programming elements. The first generation of antifuse FPGAs used antifuses that were built directly in contact with the silicon substrate itself. The second generation moved the antifuse to the metal layers to utilize what is called the Metal-to-Metal Antifuse. These antifuses function as vias. However, unlike vias that are made with the same metal that is used for the interconnection, these antifuses generally use amorphous silicon and some additional interface layers. While in theory antifuse technology could support a higher density than SRAM, the SRAM FPGAs are dominating the market today. In fact, it seems that no one is advancing antifuse FPGA devices any longer.
One of the ongoing disadvantages of antifuse technology has been their lack of re-programmability. Another disadvantage has been special silicon manufacturing processes required for the antifuse technology, which results in extra development costs and the associated time lag with respect to baseline integrated circuit (IC) technology scaling. High voltage (HV) programming currents and voltages are another major obstacle for metal-to-metal (M2M) antifuse scaling. HV circuitry can even take 60% or more of the die area.
In view of the foregoing, improved antifuse technology would have considerable potential utility. Various embodiments of the current disclosure describe a re-programmable antifuse technology that can be reprogrammed many times and be integrated into a complementary metal oxide semiconductor (CMOS) process.